Safe operating area energy limit system and method in power application

ABSTRACT

A circuit protective system with an input for sensing a reference current and an input for sensing a reference voltage. The system also has circuitry for determining an estimated energy in response to the reference current and the reference voltage and circuitry for generating a control signal responsive to the estimated energy exceeding a threshold.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to, the benefit of the filing date of,and hereby incorporates herein by reference, U.S. Provisional PatentApplication 62/199,711, entitled “Energy Limit Technique to OperatePower FETs within SOA Boundary,” and filed Jul. 31, 2015.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not Applicable.

BACKGROUND OF THE INVENTION

The preferred embodiments relate to electronic power driven systems,such as those driven with power field effect transistors (FETs).

The factors involved in certain FET power applications may conflict withone another, in terms of sufficiently sourcing power while protectingcomponent longevity. For example, some electronically-driven powerdevices have high transient demands, such as at cold start-up, whichtend toward requiring high current flow to meet the device (or customer)demands. However, high current flow can cause stress, damage, and faultviolations to power driving circuitry, including one or more FETs.Certain prior art approaches have evolved in an effort to balancebetween these competing factors, but such approaches are notparticularly ideal in some applications. For example, in automotive bodymodule applications, such as energizing an incandescent bulb coil atcold temperatures, very high peak in-rush current may be required toinitially drive the coil, such as current demands in the range ofapproximately 90 A to 100 A. Typically, a high-side power FET is used asswitch to allow this much current to flow, and in order to meet the highdemands, any limit on current flow must be higher than the expecteddemand. Hence, a level of protective circuitry may be included thatdisables current flow in response to instantaneous current or powerexceeding a set threshold, but the application dictates a high currentthreshold. Such a threshold, therefore can lead to very high voltageacross the FET in instances other than the in-rush event. For example,if a true short-circuit develops in the load, then large amounts ofcurrent may flow within the limit of the protective circuitry, whilethat current is sourced immediately to ground via the short. As anotherexample, where the load is inductive, as can be the case for a longcable short, then there may be a sudden negative voltage spike thatcauses a high drain-to-source voltage across the FET that is driving theinductive load, when that FET is disabled which is a condition known asfly-back, or the FET otherwise can accumulate excessive energy that cancause stress or damage to the FET. Thus, by implementing a higher limit,then stress/damage or other violations of the safe operating area (SOA)boundary violations of the FET may occur during switch turn-on, switchturn-off, and other events.

The above-described automotive application may suffer an additionaldrawback if addressed with the prior art instantaneous current or powerprotective circuit. Specifically, the instantaneous nature of such acircuit causes a shutdown of current flow when the monitored thresholdis exceeded, followed typically by a delay and retry, that is, wherepower is restored following the threshold-detection. However, if thecurrent demands of the circuit rise quickly yet for a short time, theprotective circuit may immediately respond by disabling current flow,then retry only to repeat the disablement, with the process causingrepeated failures in sourcing current that is otherwise needed fornormal operation of the application.

Given the preceding, while the prior art approaches may be acceptable incertain implementations, some applications may have requirements thatare not satisfactorily met with these prior art approaches.Alternatively, such approaches may be deemed unacceptable to anelectronics customer seeking to implement an application. Thus, thepresent inventors seek to improve upon the prior art, as furtherdetailed below.

BRIEF SUMMARY OF THE INVENTION

In a preferred embodiment, there is a circuit protective system. Thesystem comprises an input for sensing a reference current and an inputfor sensing a reference voltage. The system also comprises circuitry fordetermining an estimated energy in response to the reference current andthe reference voltage. The system also comprises circuitry forgenerating a control signal responsive to the estimated energy exceedinga threshold.

Numerous other inventive aspects are also disclosed and claimed.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 illustrates a preferred embodiment system 10 for controlling thesupply of power based on energy determinations.

FIG. 2 illustrates a typical prior art plot of current and voltagelimits for a transistor.

FIG. 3 illustrates a preferred embodiment safe operating area (SOA)energy profile plot, derived, for example, from a set of I/V curves fora transistor.

FIG. 4 illustrates an electrical block diagram of energy SOA detectioncircuit 16 of FIG. 1, in greater detail.

FIG. 5 illustrates a schematic of a preferred embodiment forimplementing PCO 16 e, as introduced in FIG. 4.

FIG. 6 illustrates an electrical block diagram with greater detailsshown for energy calculator and comparator 16 f and SOA table 16 a, asintroduced in FIG. 4.

FIG. 7 illustrates a timing diagram depicting a relationship between atime window count TWC₃ and an accumulated value ACC_(V) in anaccumulator.

FIG. 8 repeats the illustration of FIG. 3, but adds an energy plot lineEPL₁ to demonstrate a first example of the SOA location of an energyprofile of load current I_(L) through a load.

FIG. 9 repeats the illustration of FIG. 3, but adds an energy plot lineEPL₂ to demonstrate a second example of the SOA location of an energyprofile of load current I_(L) through a load.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG. 1 illustrates a system 10 that controls the supply of power basedon energy determinations, as is introduced in electrical block form inFIG. 1 and further detailed throughout this document. System 10 includesa digital core 12, which may be constructed of various devices so as toachieve the functionality described below. For example, digital core 12may be implemented as part of a processor (including appropriateprogramming) or as an integrated circuit module, akin in some respectsto commercially available power controllers that are used in connectionwith thermal or power detection of an associated power transistor. Onecontemporary example for such a power controller is the TPS2482 sold byTexas Instruments Incorporated, so the functionality of that device maybe further augmented by including additional circuitry and control toaccomplish the operational aspects described herein.

Looking to device connectivity in FIG. 1, digital core 12 is poweredbetween a DC reference voltage VCC, which is sometimes referred to byother conventions, such as VBB if battery power provides the voltage,and ground. Digital core 12 is connected as detailed below to a powertransistor 14, such as an n-channel MOSFET, for sensing energy throughthat device and selectively enabling its gate to turn on or off thetransistor. Digital core 12 includes an energy safe operating area (SOA)detection circuit 16 that evaluates energy across transistor 14 and inresponse communicates a FAULT signal to an ALERT input of a controlblock 18. In response, control block 18 controls a GATE enable output,connected to a gate of power transistor 14, so that digital core 12 canselectively apply a gate bias to enable or disable the current paththrough transistor 14, and as detailed later, so as to reduce the stressand potential damage to the power transistor based on conditionsdetected by energy SOA detection circuit 16. Additionally, control block18 has an input(s) to receive an alternative fault condition(s), whichcould be based on instantaneous current, whereby such a currentdetection circuit can be connected to sense the potential at a sensinginput S₁ for sensing the potential at a node N₁ and to sense thepotential at a sensing input S₂ for sensing the potential at a node N₂,whereby the current I_(L) between those nodes is thereby ascertainableby the detection circuit, such as by dividing the potential betweenthose nodes (i.e., across resistor R_(REF) as sensed between inputs S₁and S₂) by the known resistance of that resistor. In this manner,therefore, the instantaneous current detection circuit can alert block18, via the alternative fault conditions input, if the sensed currenthas exceeded a given limit. Note that other alternative fault conditionsalso may be monitored, and block 18 alerted, if a respective conditionexceeds a threshold, including power and/or thermal monitoring. In allevents, therefore, when block 18 is so alerted, it also may selectivelyassert its GATE control to turn on/off transistor 14 in response tothese conditions as well. Transistor 14 is connected to drive a load 20,where, for example, load 20 may include an inductive element. Forexample, and as introduced earlier in the Background of the Inventionsection, load 20 may include a long cable, which may have inductiveproperties. A preferred embodiment is particularly well-suited for sucha load and for the power FET driving it. In the example illustrated inFIG. 1, load 20 is connected between ground and the source and body oftransistor 14. The drain of transistor 14 is connected to a first nodeN₁ of a reference resistor R_(REF), and a second node N₂ of resistorR_(REF) is also connected to VCC. Energy SOA detection circuit 16 hasthree sensing inputs, a first S₁ for sensing the potential at secondnode N₂ of resistor R_(REF), a second S₂ for sensing the potential atfirst node N₁ of resistor R_(REF) (and hence also the drain oftransistor 14), and a third S₃ for sensing the source voltage oftransistor 14.

The operation of system 10 is now introduced, and is further detailed inthe remainder of this document. In general, when transistor 14 isenabled, it sources current I_(L) to load 20, so in the case where theload is an incandescent bulb, then in proper operation current I_(L)will satisfy the load start-up requirements, such as a relatively largein-rush current needed for a cold start. Further, I_(L) will thereaftersatisfy the generally-static requirements of current for the bulb onceits filament is heated. Further in this regard, however, energy SOAdetection circuit 16 senses, via its sensing inputs S₁ and S₂, thecurrent I_(L) through transistor 14 when that transistor is enabled, andcircuit 16 also senses, via its sensing inputs S₂ and S₃, the voltageacross transistor 14 when that transistor is enabled. The product ofthese two sensed parameters (or a scaled version thereof) representspower, and further in a preferred embodiment, circuit 16 evaluates thetrend of this power over time, that is, the transistor energy. Also in apreferred embodiment, energy limits are established and circuit 16compares monitored energy to such limits, whereby circuit 16 is operableto detect a condition representing an amount of energy across transistor14 that may provide unsafe operation, that is, exceeding a safeoperating area for the device. In response to detecting an unsafe energycondition, circuit 16 asserts a FAULT signal that is coupled as an ALERTinput to control block 18. In response, control block 18 will disablethe GATE output, thereby disabling transistor 14 for a period of time,preferably until the FAULT signal is no longer asserted by circuit 16.These operations, therefore, seek to keep the stress and potentialdamage to transistor 14 within safe boundaries, while still permittingsatisfactory operation of load 20. One skilled in the art willappreciate these and numerous other aspects, from various additionalteachings detailed below.

According to a preferred embodiment, energy SOA detection circuit 16stores an SOA table 16 a that includes data representative of safeoperating area limits for energy to be imparted across transistor 14.Such data may be stored in various forms (e.g., electronic storage, suchas internal permanent or programmable memory), and note therefore thatthe term “table” is used simply as a reference to a collection ofinformation against which comparisons are made as further detailedherein. By way of introduction in this regard, circuit 16 monitors timewindows, and an accumulation, of energy measures and compares thesevalues to those in table 16 a, so as to determine if the SOA isbreached, in which case a FAULT may be asserted by circuit 16 to controlblock 18. Note that in a preferred embodiment, the values in table 16 amay be established given various information about the SOA fortransistor 14, as further discussed below.

To further illustrate the nature of the data in table 16 a, FIG. 2illustrates a typical prior art plot of current and voltage limits for atransistor, as is often provided in literature (e.g., a datasheet) thatis available for users of the device. Particularly, FIG. 2 illustratestransistor drain-to-source voltage (V_(DS)) across its horizontal axis,and transistor drain-to-source current (I_(DS)) across its verticalaxis, both in logarithmic scales. Four different plots P₁, P₂, P₃, andP₄, are also shown, where each plot P_(x) corresponds to a differentamount of time at which the current/voltage values are imposed on thetransistor. For example, plot P₁ illustrates the transistor operationfor a period of 100 μs, where, for example, the plot at a point P_(1.1)depicts a limit of operation for a V_(DS) of 100V and an I_(DS) of 60 A,and the plot P₁ at a point P_(1.2) depicts a limit of operation for aV_(DS) of 30V and an I_(DS) of 400 A. Similarly, plot P₃ illustrates thetransistor operation for a period of 10 ms, where, for example, the plotat a point P_(3.1) depicts a limit of operation for a V_(DS) ofapproximately 100V and an I_(DS) of approximately 1.8 A, and the plot P₃at a point P_(3.2) depicts a limit of operation for a V_(DS) of 30V andan I_(DS) of 400 A. As would be appreciated by one skilled in the art,therefore, for shorter periods of time of operation, the transistor maysustain relatively larger amounts of V_(DS) and/or I_(DS), as compare tolonger periods of operation. Indeed, the limits depicted by FIG. 2 arerepresentative of the types of measures utilized by certain existingpower controllers in which case a transistor is selectively enabled anddisabled, solely based on the I/V (i.e., power) limits depicted in theplots. As detailed below, however, a preferred embodiment furthercontemplates measures of energy, that is, power over time, rather thanlimiting operation based on instantaneous power.

Given the preceding, FIG. 3 illustrates a preferred embodiment SOAenergy profile plot, derived, for example, from a set of I/V curves fora transistor, as shown in one instance in FIG. 2. More particularly,FIG. 3 illustrates time across its horizontal axis on a logarithmicscale, and transistor energy across its vertical axis. An SOA boundarySOAB is also shown in FIG. 3, whereby an unsafe operating region UORappears above boundary SOAB, and a safe operating region SOR appearsbelow boundary SOAB. In a preferred embodiment, the SOAB energy plot isderived by integration of pulse power SOA data that is typicallyprovided by an FET manufacturer, as shown by the diagonal power lines P₁to P₄ in FIG. 2. For example, P₁ is higher power than P₄, but it has tohave shorter duration for the device to be within SOA. This dataprovides the maximum power for increasing pulse durations, so that fromeach pulse duration, maximum energy can be calculated. Accordingly, theFIG. 3 SOAB is the composite of maximum energies for these pulsedurations. In any event, in general, therefore, system 10 operates sothat detection circuit 16 monitors the energy across transistor 14 andprovides control, via the FAULT signal, so that transistor 14 is enabledonly to operate in safe operating region SOR. If such energy fallswithin the unsafe operating region UOR, then FAULT is asserted andreceived by control block 18 as an ALERT, and control block 18 respondsby disabling transistor 14 via its GATE output, with the possibility ofretrying or re-enabling transistor 14 at a time when FAULT is no longerasserted by detection circuit 16. Various preferred embodiment aspectsfor providing such detection and control are provided below.

FIG. 4 illustrates an electrical block diagram of energy SOA detectioncircuit 16 of FIG. 1, in greater detail. Each of the blocks in FIG. 4 isdescribed below, where one skilled in the art may ascertain variousmanners of implementing some of those blocks (e.g., in circuitry,software, firmware, or a combination thereof), while additional detailwith respect to certain of such implementation is provided later.Looking at the general connectivity and functionality in FIG. 4, sensinginputs S1 and S2 are connected to a first voltage to current (V2I)converter 16 b. Because sensing inputs S1 and S2 provide voltagesrepresentative of the drain-to-source current through transistor 14,then V2I converter 16 b thereby provides a current output that isdesignated as IIDS, representative of that voltage. Similarly, sensinginputs S2 and S3 are connected to a second voltage to current (V2I)converter 16 c. Because sensing inputs S2 and S3 provide voltagesrepresentative of the drain-to-source voltage of transistor 14, then V2Iconverter 16 c thereby provides a current output that is designated asIVDS, representative of that voltage. Note that voltage-to-currentconverters are well-known and thus one skilled in the art may selectfrom various conventional architectures so as to implement such circuitsand their respective functionality. Each respective output of converters16 b and 16 c is connected to a multiplier 16 d, which multiplies thosetwo inputs; since one input represents transistor current and the otherrepresents transistor voltage, the product is representative of power,as indicated in the output, IPWR, from multiplier 16 d. Currentmultipliers are also well-known and once again, therefore, one skilledin the art may select from various conventional architectures so as toimplement the multiplier circuit and functionality, such as in a bi-CMOStransistor design. The output, IPWR, from multiplier 16 d, is connectedas an input to what is referred to herein as a power controlledoscillator (PCO) 16 e, which as this descriptor suggests, provides anoutput oscillating signal, fPCO, that has a frequency proportional tothe level of power represented in the input of IPWR, that is, the largerIPWR, the faster the output oscillating signal, fPCO. The outputoscillating signal, fPCO is connected to an energy calculator andcomparator 16 f, which also receives as an input the data from SOA table16 a, which was introduced earlier in connection with FIG. 3. Thecalculating portion of block 16 f calculates an energy determinationbased on power over time, where the power indication is from fPCO. Thecomparator portion of block 16 f compares the calculated energy to datain SOA table 16 a, so as to determine at different time periods whetherenergy across transistor 14 exceeds the FIG. 3 boundary SOAB. Thus,block 16 f ultimately asserts the FAULT signal if energy calculatedfalls within the unsafe operating region UOR of FIG. 3, or it de-assertsthat FAULT signal if such energy is within the safe operating region SORof FIG. 3. Control block 18, therefore, may respond as describedearlier, in response to the FAULT signal, as is also illustrated laterby way of depicting an anticipated favorable operation and resultachieved by a preferred embodiment.

FIG. 5 illustrates a schematic of a preferred embodiment forimplementing PCO 16 e, introduced above in FIG. 4. The I_(PWR) input isconnected as a current source to the drain of a first n-channel fieldeffect transistor (FET) 100, which has its source connected a node 102and its gate connected both to its source and also to a gate of a secondn-channel FET 104. The source of second FET 104 is connected to node102, which is connected to a second reference potential, such as ground,and the drain of second FET 104 is connected to a node 106. A capacitor108 is connected between node 108 and a node 110, where node 110 isfurther connected to the DC reference voltage VCC. Node 110 is alsoconnected to the source of a p-channel FET 112, which has its drainconnected to node 106 and its gate connected to an output of a delaycircuit 114. The input of delay circuit 114 is connected to the outputof a comparator 116. A non-inverting input of comparator 116 isconnected to node 106, and an inverting input of comparator 116 isconnected to a reference voltage V_(REF). The output of comparator 116is, as mentioned before, connected to the input of delay circuit 114,and it also provides the signal output of PCO 16 e, that is, thefrequency f_(PCO), which as further demonstrated below is a frequencycontrolled waveform controlled by the level of the input I_(PWR).

The operation of PCO 16 e is now described. Initially, comparator 114receives V_(REF) and as a result outputs a low signal, which afterpassing through the delay of delay circuit (e.g., 30 to 50 nsec) reachesthe gate of PMOS transistor 112, thereby enabling that device. Theenabled PMOS transistor 112 conducts VCC to node 106, therebyprecharging that node. The precharged node 106 also inputs to thenon-inverting input of comparator 116, thereby causing it to output ahigh value, which after passing through delay circuit 114 disables PMOStransistor 112, while capacitor 108 maintains the precharge voltage atnode 106. Next, as input I_(PWR) rises, FET 100 conducts and the currentis also mirrored through FET 104, thereby creating a discharge of node106, where the discharge rate is responsive to the RC effect fromcapacitor 108 and the resistance of NMOS transistor 104, to the extentthat resistance is controlled by the level of I_(PWR). From thisdischarge, eventually the voltage at node 106 falls below V_(REF), inwhich case again the output of comparator 116 transitions to low, whichafter passing through the delay of delay circuit 114 again enables PMOStransistor 112, thereby repeating the process described above. Given thepreceding, therefore, one skilled in the art will appreciate that theoutput of PCO 16 e, f_(PCO), provides a transitioning signal with afrequency that may be generally represented by the following Equation 1:

$\begin{matrix}{f_{PCO} = {\frac{{C(108)} \times V_{REF}}{I_{PWR}} + \Delta}} & {{Equation}\mspace{14mu} 1}\end{matrix}$where,

C(108) is the capacitance of capacitor 108; and

Δ is the delay of a one-shot reset circuit (not separately shown) thatresets the input node (capacitor) of comparator 116. Note that Δ alsosets the width of output pulses of PCO 16 e.

For sake of later discussion, note that during normal operation whereoperation of system 10 is occurring within the safe operating area(i.e., region SOR in FIG. 3), the period of f_(PCO) is expected to be atleast 512 μsec by way of example, and this is noted because, as furtherdetailed below, the preferred embodiment examines f_(PCO) over time anda shorter f_(PCO) period may well be interpreted as a fault condition,

FIG. 6 illustrates an electrical block diagram with greater detailsshown for energy calculator and comparator 16 f and SOA table 16 a. Eachof the blocks in FIG. 6 is described below, where one skilled in the artmay ascertain various manners of implementing those blocks (e.g., again,in circuitry, software, firmware, or a combination thereof). In apreferred embodiment, the signal f_(PCO) is input to energy calculatorand comparator 16 f and more particularly to a counter 200, which in theexample shown is a 2-bit counter. Counter 200 counts each periodtransition of the signal f_(PCO), and the count is reset by theassertion of a clock CLK. For reasons evident below, CLK is assertedevery 100 nsec and, therefore, counter 200 counts and then resets foreach successive 100 nsec period. Note also that counter 200 may beimplemented as a Gray code counter, so as to avoid Nyquist limitationsthat may arise if the system clock (not shown) frequency is relativelyclose to the event being counted (i.e., period transitions in f_(PCO))and to save significant capacitor area. Note that only 2 bits are neededfor a count up to four, as in the example provided normal operationsshould yield a count no greater than four for the period being counted;of course, in other instances, such as where larger current demands areanticipated, the number of bits in counter 200 may be increased. Thecount output of counter 200 is connected to a first time window blockTW₁.

First time window block TW₁, from an initial reset state and assynchronized by the CLK signal for every 80 CLK periods, adds to itscurrent count each count value received from counter 200. Thus, 100 nsecafter a reset, first time window block TW₁ receives a first count fromcounter 200, and thereafter for a count instance that extends until thenext reset of block TW₁, block TW₁ adds to its count total eachsuccessive count received from counter 200 during that count instance.As a result, for a number of iteratively received counts from counter200, block TW₁ develops a total count corresponding to a time window forblock TW₁. For example, this iterative operation is represented in thefollowing Equation 2:TW₁ counts=Σ_(i=1) ⁸⁰(100 nsec counts from counter 200)  Equation 2Equation 2 is intended to indicate that, after a reset by asserting aclock CLK, counter 200 counts for a 100 nsec period, and that countconcluding the 100 nsec period is output to first time window block TW₁;block TW₁ stores this first post-reset count as a total, and thereafterit adds to its total each additional consecutive 100 nsec count fromcounter 200, for a total of i=80 iterations, where the first iterationis the initial total from counter 200 followed by 79 adds thereafter.Hence, block TW₁ sums the counts received from counter 200 over an(i=80)*100 nsec=8 μsec time window period. Once block TW₁ concludes itssummation over i=80 iterations, it outputs the summed number of countsTWC₁ to a threshold comparison block 202 and also to a second timewindow block TW₂. Thereafter, block TW₁ resets in synchronization withthe next CLK signal, and it receives its next initial count from counter200 and repeats the process described above, again to total a next setof i=80 counts received from counter 200.

Second time window block TW₂ operates in a comparable manner to firsttime window block TW₁ described above, but block TW₂ adds counts over alonger respective time window. For block TW₂, from an initial resetstate and as synchronized by the CLK signal for every 1,280 CLK periods(i.e., 1,280*100 nsec=128 μsec), block TW₂ adds to its current counteach count value received from block TW₁. Thus, after a block TW₂ reset,second time window block TW₂ receives a first count from block TW₁, andthereafter for a 128 μsec count instance that extends until its nextreset, block TW₂ adds to its total each successive count received fromblock TW₁ during that count instance. As a result, for a number ofiterations, block TW₂ develops a total count corresponding to a timewindow for block TW₂, and this iterative operation is represented in thefollowing Equation 3:TW₂ counts=Σ_(i=1) ¹⁶(8 μsec counts from block TW₁)  Equation 3Equation 3 is intended to indicate that, after a resetting instance froma transition of CLK, block TW₂ stores a first post-reset count fromblock TW₁ as a total, and thereafter for 15 more iterations block TW₂adds to its total each additional consecutive 8 μsec count from blockTW₁, for a total of i=16 iterations of count values received from blockTW₁. Hence, block TW₂ sums the counts received from block TW₁ over a 128μsec time window period. Once block TW₂ concludes its summation overi=16 iterations, it outputs the summed number of counts TWC₂ tothreshold comparison block 202 and also to a third time window blockTW₃. Thereafter, block TW₂ resets in synchronization with the next CLKsignal, and it receives its next initial count from block TW₁ andrepeats the process described above, again to total i=16 count valuesreceived from block TW₁.

Third time window block TW₃ operates in a comparable manner to first andsecond time window blocks TW₁ and TW₂ described above, but block TW₃adds counts over still a longer time window. For block TW₃, from aninitial reset state and as synchronized by the CLK signal for every10,240 CLK periods (i.e., 10,240*100 nsec=1,024 μsec), block TW₃ adds toits current count each count value received from block TW₂. Thus, aftera block TW₃ reset, third time window block TW₃ receives a first countfrom block TW₂, and thereafter for a 1,024 μsec count instance thatextends until its next reset, block TW₃ adds to its total eachsuccessive count received from block TW₂ during that count instance. Asa result, for a number of iterations, block TW₃ develops a total countcorresponding to a time window for block TW₃, and this iterativeoperation is represented in the following Equation 4:TW₃ counts=Σ_(i=1) ⁸(128 μsec counts from block TW₂)  Equation 4Equation 4 is intended to indicate that, after a resetting instance froma transition of CLK, block TW₃ stores a first post-reset count fromblock TW₂ as a total, and thereafter for 7 more iterations block TW₃adds to its total each additional consecutive 128 μsec count from blockTW₂, for a total of i=8 iterations of count values received from blockTW₂. Hence, block TW₃ sums the counts received from block TW₂ over a1,024 μsec time window period. Once block TW₃ concludes its summationover i=8 iterations, it outputs the summed number of counts TWC₃ tothreshold comparison block 202 and also to an accumulator 204.Thereafter, block TW₃ resets in synchronization with the next CLKsignal, and it receives its next initial count from block TW₂ andrepeats the process described above, again to total i=8 count valuesreceived from block TW₂.

Accumulator 204 receives count TWC₃ from third time window block TW₃ andadds that to any earlier received value from block TWC₃, withoutresetting under normal operations. Thus, over successive 1,024 μsec timewindows for block TW₃, if block TW₃ outputs a non-zero count, then thevalue in accumulator 204 may tend to increase from successive non-zerovalues received from block TW₃. In addition, however, accumulator 204further operates to decrement its accumulated count at a fixedfrequency, which in a preferred embodiment example is a decrement of onecount per 512 μsec. In this regard, recall that third time window blockTW₃ produces a new count output for count TWC₃, every 1,024 μsec. Ineffect, therefore, accumulator 204 will decrement that count a firsttime, halfway along the period at which it is receiving counts from timewindow block TW₃, and it will decrement again a second time, 512 μsecafter the halfway point, so as to decrement twice during each 1,024 μsecperiod. Further, the count value ACC_(V) accumulated in accumulator 204is also input to threshold comparison block 202.

To further illustrate the operation of accumulator 204 and itsrelationship to the count TWC₃ from block TW₃, FIG. 7 illustrates atiming diagram with 512 μsec increments between timing events t₀, t₁, .. . t₁₀. A top plot illustrates an example of a respective count TWC₃for third time window block TW₃ as determined at each of its 1,024 μsectime windows, and a bottom plot illustrates the corresponding example ofthe respective accumulated value ACC_(V) in accumulator 204. By way ofexample, therefore, following a reset at time t₀, block TW₃ begins tocount and reaches a count of TWC₃=2 by the completion of its first 1,024μsec time window, as shown at time t₂; meanwhile, accumulator 204 isreset to a value ACC_(V) of 0. At time t₂, block TW₃ resets its count toa value of 0 (as shown above the vertical dashed time line at t₂), whileat the same time accumulator 204 receives the count of TWC₃=2 and addsit to its current accumulated value of 0 for a total of 2+0=2, while inaddition accumulator 204 decrements by one every 512 μsec, so at thesame time this amount is reduced by 1, leaving a total value ofACC_(V)=2+0−1=1 counts remaining in accumulator 204 immediatelyfollowing time t₂. Once 512 μsec again expires after time t₂, that is,as of time t₃, then accumulator 204 again decrements by 1, at whichpoint its accumulated value ACC_(V) is reduced to 1−1=0. Meanwhile,block TW₃ continues to count during its second 1,024 μsec time windowbetween times t₂ and t₄, and in the example illustrated, again duringthis time window TWC₃ reaches a value of 3, as shown immediately beforetime t₄. At time t₄, block TW₃ again resets its count to a value of 0,while at the same time accumulator 204 receives the count of TWC₃=3,adds it to its current accumulated value of 0 and decrements by 1, sothe total of ACC_(V)=3+0−1=2 remains in accumulator 204 immediatelyfollowing time t₄. Continuing the illustrated example, once 512 μsecagain expires after time t₄, that is, as of time t₅, then accumulator204 again decrements by 1, at which point its accumulated value isreduced to ACC_(V)=2−1=1, and meanwhile block TW₃ continues to countduring its third 1,024 μsec time window between times t₄ and t₆ and inthe illustrated example TWC₃ again reaches a value of 3, as shownimmediately before time t₆. At time t₆, block TW₃ again resets its countto a value of 0, while at the same time accumulator 204 receives thecount of TWC₃=3, adds it to its current accumulated value of 1 anddecrements by 1, so the total of ACC_(V)=3+1−1=3 remains in accumulator204 immediately following time t₆.

Given the preceding, one skilled in the art should appreciate theongoing operation of accumulator 204 and its relationship with thepreceding time window blocks TW₁, TW₂, and TW₃. Each time window blockTW_(x) amasses a count corresponding to the number of period cycles infrequency f_(PCO) during a respective time window, and ultimatelyaccumulator 204 has a value that rises with a greater number of countsbut may steadily fall by its auto-decrement for each successive 512 μsecperiod. If TWC₃ remains near or at zero, therefore, the decrementing ofaccumulator 204 will keep its value also near zero. However, if TWC₃remains at a value of 3 (or above), note therefore that the accumulatorvalue will steadily increase, as its decrementing twice during each1,024 μsec time window for block TW₃ will be insufficient to return theaccumulated value toward 0. In this regard, for example, note furtherthe continuing example in FIG. 7 at times t₇ and t₈. Specifically, attime t₇, accumulator 204 decrements its value from 3 to 2, but at timet₈, the TWC₃ value of 3 is added to the accumulated value of 2 and thendecremented, leaving a value of 4 in accumulator 204. A similaroccurrence happens at time t₁₀, so note in this pattern the accumulatedvalue will continue to climb. The preferred embodiment consequences tosuch a climb, as well as the remaining blocks and operation of the FIG.6 comparator 16 f and SOA table 16 a, are further discussed below.

Given the preceding, one skilled in the art may readily appreciate thateach of the time window counts TWC₁, TWC₂, and TWC₃ represent areal-time measure proportional to load energy, that is, proportional tothe amount of load current I_(L) (see, FIG. 1) that has been sensed overa corresponding amount of time, where the time depends on the timewindow per each of blocks TW₁, TW₂, and TW₃. For example, as block TW₁counts over time, it is in effect counting a signal (i.e., f_(PCO))representative of load current I_(L) flow during that time; moreover,therefore, and as known in the art, current over time represents energy.Each of the remaining time window blocks operates similarly, and theaccumulator value ACC_(V) also is such a representation, albeit one thatcan decrement over time periods when load current is relatively low, yetwill also increase and continue to increase, without fully decrementing,if load current is relatively high. Thus, the calculating portion ofblock 16 f includes numerous stages that measure energy over differentrespective time periods.

Given the preceding observations, and returning to FIG. 6, thresholdcomparison block 202 also receives time window limit values TWL_(x) andan accumulator value ACCL from SOA table 16 a. In a preferredembodiment, each time window limit value TWL_(x) corresponds to arespective time window count TWC_(x), that is: (1) time window limitvalue TWL₁ corresponds to a respective time window count TWC₁; (2) timewindow limit value TWL₂ corresponds to a respective time window countTWC₂; and (3) time window limit value TWL₃ corresponds to a respectivetime window count TWC₃. Lastly, accumulator value ACCL corresponds tothe count value ACC_(V) in accumulator 204. Given these correspondingvalues, threshold comparison block 202 operates to compare each pair ofrespective corresponding values and to assert the FAULT signal if anycount TW_(x) or ACC_(V) exceeds its respective limit TWL_(x) or ACCL.Thus, in a preferred embodiment, one skilled in the art establishes arespective number for each of the values of TWL_(x) and ACCL thatcorresponds to a sufficiently large number of counted or accumulatedcycles of f_(PCO), which thereby also corresponds to a relatively largeamount of energy, as driven by the load current I_(L) over time. Inother words, the combined blocks in FIG. 6 provide a staged thresholdcomparison block 202 which, in effect, permits analysis of energyevaluation for a relatively short time (i.e., TW₁) relative to the limitTWL₁, a medium amount of time (i.e., TW₂) relative to the limit TWL₂, ora relatively longer time (i.e., TW₃) relative to the limit TWL₃, alongwith an ongoing accumulation over all ongoing operational time, betweenoverall circuit resets, or the like (i.e., ACC_(V) relative to ACCL). Solong as each of the evaluated values remains within its respectivelimit, then FAULT is not asserted and power transistor 14 remainsenabled, thereby sourcing load current I_(L) to load 18. If, however,any of the evaluated values exceeds its respective limit, then FAULT isasserted and, as described earlier, control block 18 receives the FAULTas an ALERT and operates via its GATE output to disable the conductivityof power transistor 14, thereby potentially protecting the load 20 orthe power transistor 14 from excessive energy events that otherwisecould unduly stress or damage those devices. Moreover, in a preferredembodiment, once the FAULT signal is asserted, it continues to beasserted until all values TWC₁ through TWC₃ and ACC_(V) return to zero.Thereafter, FAULT is de-asserted, at which time control block 18 mayretry, that is, re-enable the GATE signal to power transistor 14. Below,such operation and resulting benefits are further illustrated, by waysof example.

As a numerical example, assume that under a given state of operation,for transistor 14, I_(DS)=108a and V_(DS)=48V, so that power=108×48≈5.2kW. Assume also that through converters 16 b and 16 c, these I_(DS) andV_(DS) values convert, respectively, to I_(IDS)=4 μA and I_(VDS)=4 μA.Moreover, assume that the product of these powers, as input to PCO 16 evia I_(PWR), results in f_(PCO)=1.75 MHz. Each PCO cycle, therefore,represents 5.2 kW/1.75 MHz=3 mJ energy. Thus, in order to fault detectbeyond a limit of 100 mJ for a 128 μsec period, then TWL₂ is set to 100mJ/3 mJ≈33 counts. In other words, since time window block TW₂ accruescounts over a 128 μsec period, then so long as those counts are 33 orbelow, then 100 mJ of energy has not been measured during that period;if, however, the count TWC₃ exceeds 33, then energy has exceeded 100 mJ,and the FAULT is asserted as described above. Of course, the abovenumbers are only by way of example, and one skilled in the art mayappreciate numerous other examples and conditions, as well as comparableapplicability to other time windows and to accumulator 204

FIG. 8 repeats the illustration of FIG. 3, but adds an energy plot lineEPL₁ (shown as a dashed line) to demonstrate an example of the energyprofile of load current I_(L) through load 20. Note that plot line EPL₁has a peak EPL_(1.P) that may occur at power-up, when driving anincandescent bulb as the load at low temperature (e.g., −40° C.), andindeed note further that the energy profile rolls off after peakEPL_(1.P), thereby representing that after a certain time driving abulb, the continuing drive energy expended is less than thepackage/assembly is able to dissipate, so the dissipation therebyreduces the accumulated energy on the device going down to zero for longterm operation. Looking before the roll-off at peak EPL_(1.P), it mayoccur when current I_(L) experiences what is considered an in-rush levelfor a relatively short period of time, during which the real-timecurrent magnitude may exceed the manufacturer specification or datasheetcurrent. Indeed, in a prior art implementation, an in-rush event maycause a power controller to turn off the power transistor through whichthe current is provided, as instantaneous current at that time and givencircuit temperature, may be too excessive (see, e.g., FIG. 2). In thepreferred embodiment, however, because the energy of the current overtime is evaluated and used as a condition to control the transistor,then even at peak EPL_(1.P) the amount of energy is still within thesafe operating region SOR (i.e., below SOAB) and, therefore, thetransistor remains on and current is continuously provided to load 20(e.g., bulb). In other words, in terms of FIG. 6, even withinstantaneous high current levels, the time-related counts within blocksTW₁ through TW₂ and accumulator 204 remain below their respective limitsTWL₁ through TWL₃ and ACCL. Thus, the preferred embodiment is operableto maintain current I_(L) in conditions where the prior art woulddisable it. Moreover, one skilled in the art also should now furtherappreciate the effect of the counts and decrementing in accumulator 204.Specifically, once a limit is exceeded, FAULT is asserted, andtransistor 14 is gated off, accumulator 204 may still contain counts andthey will only diminish as additional time passes, so that each count isdecremented at a rate of one count/512 μsec, while FAULT will thereforeremain asserted. Thus, until accumulator 204 fully decrements to zero,FAULT remains asserted and, hence, current IL is not allowed to flow aspower transistor 14 remains disabled. During this time, therefore, aretry does not occur and energy may dissipate at a controlled rate, suchas that equivalent to the rate of thermal dissipation associated witheither the integrated circuit package or printed circuit board (PCB)associated with either load 20 or the entirety of system 10. Thus, whena retry does occur, after ACC_(V) reaches zero, adequate thermal energyis also dissipated so as not to overly stress the power transistor onthe next attempted retry.

Having demonstrated various results in FIG. 8, then returning to FIG. 6one skilled in the art can now appreciate that each of the energy limitsof the values TWL_(x) and accumulator value ACCL may be set with numbersthat may be derived from the SOA boundary SOAB, according to the safeoperating energy limit shown by that boundary over different amounts oftime. With such limits, FIG. 8 illustrates an example where system 10 isoperating within the safe operating area, and note therefore that energyplot line EPL₁ always remains in safe operating region SOR. To maintainsuch operation, therefore, as each time window block periodicallyassesses energy through power transistor 14, threshold comparison block202 respectively confirms that no respective energy limit (from SOAtable 16 a) is exceeded and, hence, control block 18 continues to enablepower transistor 14. To the contrary, if any of the limits is exceeded,then I_(L) is disrupted so as to not unduly stress or potentially damagesystem components and adequate time is allotted before retry orre-enablement I_(L), so as to adequately dissipate energy again toprotect the system.

FIG. 9 repeats the illustration of FIG. 3, but has a second alternativeenergy plot line EPL₂ to demonstrate an alternative example of an energyprofile of load current I_(L) through load 20. The FIG. 9, example,however, demonstrates an instance, such as a short-circuit, where ameasure of current I_(L) increases rapidly around a time indicated att₁, that is, as shown where energy plot line EPL₂ begins to rise in anear-vertical fashion. According to one preferred embodiment, recallthat control block 18 of FIG. 1 may receive alternative faultconditions, including from a current detection circuit that monitors ameasure of the current I_(L), and that also alerts block 18 if thesensed current exceeds a given limit. In FIG. 9, therefore, such aninstance occurs at time t₁, whereby current begins to rise very quicklyand, hence, so does energy as shown in plot EPL₂. However, prior to theenergy reaching the SOAB boundary, control block 18 may alternativelyrespond to the detected condition (i.e., alternative FAULT) from thecurrent detection circuit and, in response, control block 18 disablesits GATE output, thereby disabling the gate potential to, and theoperation of, transistor 14. Thus, immediately following time t₁, FIG. 9illustrates that energy across transistor 14 begins to decline until atime t₂, which is approximately 30 msec following time t₁.

Further according to the preferred embodiment, control block 18 does notre-enable its GATE signal solely in response to the current fault beingcleared, but instead it continues to maintain its GATE output disableduntil the energy, as monitored by energy SOA detection circuit 16, fallsbelow a threshold, which threshold could be even down to a level ofzero. In contrast, in the prior art where only current may be monitoredin a context such as the one presently described, then a prior artcontrol circuit may tend to re-enable (i.e., retry) the transistor gatevery quickly, such as based solely on a measure of time, after thetransistor was disabled; in such a prior art approach, therefore,current is repeatedly turned on and turned back off, if the shortcircuit condition persists. As a result, if the prior art retry timeperiod is relatively short, additional energy accumulates across thetransistor for each of the successive turn on/off periods, that is,without ample time in each instance for such energy to dissipate, itaccumulates and thereby poses or causes damage to the transistor. Incontrast, in a preferred embodiment and as shown in FIG. 9, even if thecurrent condition is cured, or if the current detection circuitautomatically releases its fault based on a short time period after theexcessive current condition was detected, control block 18 adds theadditional protective step of awaiting dissipation of energy, as occursat time t₂. At that time, therefore, control block 18 re-enables GATEand transistor 14. In the example illustrated, however, theshort-circuit condition persists, so at time t₂, again the energy plotrises very quickly as shown by the vertical transition at that time, andin response the same response occurs as did at time t₁, namely, controlblock 18 is so notified as an alternative fault condition and transistor14 is disabled. Again, following time t₂, the retry is delayed untilenergy, as shown in plot EPL₂, dissipates all the way to zero, soanother 30 msec passes between the successive retries. In this manner,and for any additional successive retries, in each instance the amountof energy imposed across transistor 14 is limited to below the boundarySOAB. As a result, even in the instance of multiple successive retries,transistor 14 is protected, as compared to a current-only detectionapproach of the prior art.

Given the preceding, the preferred embodiments provide a beneficial andimproved electronic power driven systems, such as those driven withpower FETs. The preferred embodiments permit the power driving of a loadunder potentially high current situations, either anticipated (e.g.,cold start-up) or undesirable (e.g., short circuit), where protection isafforded of the power system while also permitting flexibility to safelyturn on a load if energy constraints associated with the system are notexceeded. Numerous other benefits arise from the preferred embodiments,and still others may be ascertained by one skilled in the art. Asfurther examples, therefore, in one implementation, load protection maybe implemented without restrictions based on, or solely on,instantaneous current or power or, as alternative so as not to stopcurrent simply in response to a real-time transient. Thus, the preferredembodiments permit peak power transients without causing SOA boundaryviolation in terms of energy. As another example, while one preferredembodiment implementation has been described in connection with anincandescent bulb in an automotive application as the load, variousother implementations will benefit. As another example, reliability isimproved by disabling the power transistor until energy is fullydissipated, and retry time depends on the energy generated on thetransistor, as will be tracked in the accumulator. As another example,SOA boundary is dynamically monitored by different temporal windows andenergy limit thresholds, so as to evaluate multiple energy limitscorresponding to different time periods. As still another example, thepreferred embodiment may be implemented with non-complex circuitry(e.g., PCO circuitry combined with a Gray-coded counter) allowing apower-to-digital conversion. In view of the above, therefore, theinventive scope is far reaching, and while various alternatives havebeen provided according to the disclosed embodiments, still others arecontemplated and yet others can ascertained by one skilled in the art.Given the preceding, therefore, one skilled in the art should furtherappreciate that while some embodiments have been described in detail,various substitutions, modifications or alterations can be made to thedescriptions set forth above without departing from the inventive scope,as is defined by the following claims.

The invention claimed is:
 1. A circuit protective system, comprising: areference current sensing input; a reference voltage sensing input;energy circuitry having inputs coupled to the current sensing input andthe voltage sensing input and having an energy output; thresholdcircuitry having an input coupled to the energy output and having afault output; and in which the energy circuitry includes oscillatorcircuitry coupled to the current sensing input and the voltage sensinginput for producing a signal at the energy output having a frequency,and the frequency is responsive to a reference current and a referencevoltage.
 2. The system of claim 1 in which the energy circuitry includesa counter for counting cycles of the signal over a first period of time.3. The system of claim 2 in which the energy circuitry includes at leastone time window circuit for summing successive counts from the counterover a second period of time greater than the first period of time. 4.The system of claim 3 in which the threshold circuitry provides a faultsignal on the fault output in response to the at least one time windowcircuit summing successive counts to exceed a threshold.
 5. The systemof claim 2: in which the energy circuitry includes time window circuits,in which each time window circuit is for summing successive counts fromthe counter over a respective different period of time; and in which thethreshold circuitry generates a threshold signal on the threshold outputin response to any one of the time window circuits summing successivecounts to exceed a threshold corresponding to the one of the of the timewindow circuits.
 6. The system of claim 5: in which the counter is forcounting during an iteration and then resetting to count for eachsuccessive next iteration; and in which the time window circuitsinclude: a first time window circuit coupled to receive a count from thecounter over a first number of counter iterations; a second time windowcircuit coupled to receive a count from the first time window circuitover a second number of counter iterations greater than the first numberof counter iterations; and a third time window circuit coupled toreceive a count from the second time window circuit over a third numberof counter iterations greater than the first number of counteriterations.
 7. The system of claim 6 and further including: anaccumulator for receiving and summing successive counts from the thirdtime window circuit; and circuitry for periodically decrementing theaccumulator.
 8. The system of claim 7 in which the threshold circuitrygenerates the fault signal in response to a sum in the accumulatorexceeding the threshold.
 9. The system of claim 8 including comparatorcircuitry for disabling flow of the reference current in response to thefault signal when the energy exceeds the threshold.
 10. The system ofclaim 9 in which the threshold includes a first threshold, and includingcomparator circuitry for re-enabling flow of the reference current,after disabling flow of the reference current, in response to the faultsignal and when the estimated energy falls below a second threshold. 11.The system of claim 8 including comparator circuitry for disabling flowof the reference current in response to the fault signal when the energyexceeds the threshold and for a duration until the accumulator isdecremented to a count of zero.
 12. The system of claim 2 in which thecounter includes a Gray code counter.
 13. The system of claim 1including comparator circuitry for disabling flow of the referencecurrent in response to the fault signal when the energy exceeds thethreshold.
 14. The system of claim 1 including a transistor having agate coupled to be selectively enabled and disabled in response to thefault signal and for conducting the reference current when enabled. 15.The system of claim 14 including a load coupled to the transistor andfor receiving a current when the transistor is enabled.
 16. The systemof claim 15 in which the load includes an incandescent bulb.
 17. Acircuit protective system, comprising: a first terminal to connect to afirst node; a second terminal to connect to a second node; currentdetermining circuitry determining a reference current between the firstnode and the second node; a third terminal to connect to a third node;voltage determining circuitry determining a reference voltage betweenthe third node and another node; energy determining circuitry estimatingenergy in response to the reference current and the reference voltage;control signal circuitry generating a control signal responsive to theestimated energy exceeding a threshold; and in which the energydetermining circuitry includes waveform circuitry producing a signalhaving a frequency, in which the frequency is responsive to a product ofthe reference current and the reference voltage.